ch1-What a testbench?

2019-10-24

What are abstraction levels ?

​ In the Preface, you saw that we toggled the design using individual signals.

#5  resetn <= 0;
#20 resetn <= 1;

​ Instead, if you put these two signals in a task and call it “apply_reset” task, you have just created a component that can be re-used and hides the details of what signals and what time intervals it is being asserted. This is a feature we would like to have when developing the testbench - to hide away details - so that the test writer need not bother about the how and instead focus on when and why these tasks should be put to use. A test writer finally uses tasks, configures environment and writes code to test the design.

module tb_top;
 
  bit resetn;
 
  task apply_reset ();
    #5  resetn <= 0;
    #20 resetn <= 1;
  endtask
 
  initial begin
    apply_reset();  
  end
endmodule

将一些操作封装成方法，这样test writer就不需要知道具体如何对接口信号操作，只需要知道什么时候应该进行什么操作就行了。