There are two types of arrays in SystemVerilog - packed and unpacked arrays.
A packed array is used to refer to dimensions declared before the variable name.
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bit [3:0] data; // Packed array or vector logic queue [9:0]; // Unpacked array
A packed array is guaranteed to be represented as a contiguous set of bits. They can be made of only the single bit data types like bit, logic, and other recursively packed arrays.
Single Dimensional Packed Arrays
A one-dimensional packed array is also called as a vector.
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module tb; bit [7:0] m_data; // A vector or 1D packed array
initialbegin // 1. Assign a value to the vector m_data = 8'hA2;
// 2. Iterate through each bit of the vector and print value for (int i = 0; i < $size(m_data); i++) begin $display ("m_data[%0d] = %b", i, m_data[i]); end end endmodule
Multidimensional Packed Arrays
A multidimensional packed array is still a set of contiguous bits but are also segmented into smaller groups.
Example #1
The code shown below declares a 2D packed array that occupies 32-bits or 4 bytes and iterates through the segments and prints its value.
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module tb; bit [3:0][7:0] m_data; // A MDA, 4 bytes
initialbegin // 1. Assign a value to the MDA m_data = 32'hface_cafe;
$display ("m_data = 0x%0h", m_data);
// 2. Iterate through each segment of the MDA and print value for (int i = 0; i < $size(m_data); i++) begin $display ("m_data[%0d] = %b (0x%0h)", i, m_data[i], m_data[i]); end end endmodule
module tb; bit [2:0][3:0][7:0] m_data; // An MDA, 12 bytes
initialbegin // 1. Assign a value to the MDA m_data[0] = 32'hface_cafe; m_data[1] = 32'h1234_5678; m_data[2] = 32'hc0de_fade;
// m_data gets a packed value $display ("m_data = 0x%0h", m_data);
// 2. Iterate through each segment of the MDA and print value foreach (m_data[i]) begin $display ("m_data[%0d] = 0x%0h", i, m_data[i]); foreach (m_data[i][j]) begin $display ("m_data[%0d][%0d] = 0x%0h", i, j, m_data[i][j]); end end end endmodule