ch3-Function
2019-10-24
Functions
The primary purpose of a function
is to return a value that can be used in an expression and cannot consume simulation time.
- A function cannot have time controlled statements like
@
,#
,fork join
, orwait
- A function cannot start a task since tasks are allowed to consume simulation time
Click here to refresh functions in Verilog !
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Simulation Log
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Click to try this example in a simulator!
Using declarations and directions
Although ANSI-C style declaration was later introduced in Verilog, the old style declaration of port directions are still valid. SystemVerilog functions can have arguments declared as input and output ports as shown in the example below.
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参数方向:input、output、inout、ref四种。
Difference between function
and task
Function | Task |
---|---|
Cannot have time-controlling statements/delay, and hence executes in the same simulation time unit | Can contain time-controlling statements/delay and may only complete at some other time |
Cannot enable a task | Can enable other tasks and functions |
Should have atleast one input argument and cannot have output or inout arguments | Can have zero or more arguments of any type |
Can return only a single value | Cannot return a value, but can achieve the same effect using output arguments |
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