SV——数据类型 SystemVerilog中扩展了Verilog中的数据类型，增加双状态数据、动态数组、队列等。 1. 内建类型1.1 logic类型SV中将reg类型替换成logic关键字，logic既可以在块语句中被赋值，也可以在assign中被赋值，可以用wire的地方都可以用logic来替换，但logic不能有多个驱动，比如双向总线建模的时候需要用wire。 1.2 双状态数据类型只有0 1两个状态，没有 2019-07-21 Verification System Verilog IC SV Verification
Cummings——异步FIFO第二讲 0. 参考Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons – Clifford E. Cummings ，Sunburst Design 1. 异步FIFO异步FIFO是指读数据在一个clock demain，写数据在另一个clock dem 2019-07-18 IC Asynchronous IC Asynchronous
Cummings——异步FIFO第一讲 0. 参考Simulation and Synthesis Techniques for Asynchronous FIFO Design — Clifford E. Cummings, Sunburst Design 1. 异步FIFO在跨时钟域传输的时候容易发生亚稳态。当在不同时钟域之间传递的多个信号时，需要用到异步FIFO。 异步FIFO的难点在于生成读写地址和空满指示位。 2. FIFO 2019-07-16 IC Asynchronous IC Asynchronous
SV——接口 1. Interface概念System Verilog中引入了接口定义，接口与module 等价的定义，是要在其他的接口、module中直接定义，不能写在块语句中，跟class是不同的。 接口是将一组线捆绑起来，可以将接口传递给module。 2. 接口的优点一）通过接口在module之间或内部进行信号，模块的输入列表就是一个接口，这样简单，避免手动连线的错误。 二）如果需要增加模块 2019-07-15 Verification System Verilog IC SV
ch1-What a testbench? 2019-10-24 What are abstraction levels ? In the Preface, you saw that we toggled the design using individual signals. 12#5 resetn <= 0;#20 resetn <= 1; Instead, if you put these two s 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch2-Enume 2019-10-24 The user can assign any integer value for any of the enumerated names. If any name does not have an assigned value, then it automatically takes the incremented value of the previous na 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch2-new data types 2019-10-24 2-state data types When a 4-state value is converted to a 2-state value, any unknown or high-impedance bits shall be converted to zeros. The most important 2-state data type is bit whic 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch2-Integers 2019-10-24 Integer Integers are numbers without a fractional part or in other words, they are whole numbers. SystemVerilog has three new signed data types to hold integer values each with a differ 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch2-String 2019-10-24 How are strings represented in Verilog ? A single ASCII character requires 8-bits (1 byte) and to store a string we would need as many bytes as there are number of characters in the str 2019-07-15 Verification System Verilog SV ChipVerif_Web