ch3-Function 2019-10-24 FunctionsThe primary purpose of a function is to return a value that can be used in an expression and cannot consume simulation time. A function cannot have time controlled statements like 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch4-Fork join 2019-10-24 三种forkWhat are different fork - join styles ?We have three different styles of fork join in SystemVerilog. fork join Finishes when all child threads are over fork join_any Finishes w 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch5-Interprocess Communication 2019-10-24 SystemVerilog Interprocess Communication Components in a testbench often need to communicate with each other to exchange data and check output values of the design. A few mechanisms tha 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch5-Semaphore 2019-10-30 SystemVerilog Semaphore Semaphore is just like a bucket with a fixed number of keys. Processes that use a semaphore must first get a key from the bucket before they can continue to exec 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch6-Clocking block 2019-11-02 SystemVerilog Clocking Blocks Module ports and interfaces by default do not specify any timing requirements or synchronization schemes between signals. A clocking block defined between 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch6-Interrface 2019-10-31 SystemVerilog InterfaceWhat is an Interface ?An Interface is a way to encapsulate signals into a block. All related signals are grouped together to form an interface block so that the same 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch6-Modport 2019-11-02 SystemVerilog Modport Modport lists with directions are defined in an interface to impose certain restrictions on interface access within a module. The keyword modport indicates that th 2019-07-15 Verification System Verilog SV ChipVerif_Web
ch7-local 2019-11-12 SystemVerilog local A member declared as local is available only to the methods of the same class, and are not accessible by child classes. However, nonlocal methods that access local m 2019-07-15 Verification System Verilog SV ChipVerif_Web
UVMPrimer中的DUT改写成Verilog 内容：讲UVMPrimer书给的代码中的DUT改写成了Verilog形式，原来时VHDL形式，用VCS仿真的时候总是出错，花了大半天改写了。 DUT介绍这本书中的DUT是个ALU，模块管脚如下图， A,B是两个八位的输入，start是启动信号，op是命令信号，包括加，乘，与等，result是计算结果，done是DUT的应答信号，当dut计算结束，done为1。ALU中的计算有单周期，也有多周期的 2019-07-10 Verification Others IC SV Verification
EasierUVM安装问题 perl包安装EasierUVM需要安装File::Copy::Recursive,File::stat, and Time::Piece modules.这几个PERL 包，官方文档给的安装命令是 123perl -MCPAN -e 'install File::Copy::Recursive'perl -MCPAN -e 'install File::stat&# 2019-07-01 tools EDA vcs IC SV vcs